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| JAN. 2000 DATA SHEET S5D2501F OSD PROCESSOR FOR MONITORS S5D2501F OVERVIEW The S5D2501F is used to display some characters or symbols on a screen of monitor. Basically, the operation is to control the internal memory on chip and generate the R,G,B signals for some characters or symbols. The R,G,B signals are synchronized with the horizontal sync. Then the R,G,B signals are mixed with the main video signal in the Video Amp IC. The font data for characters or symbols are stored in the internal ROM. This stored data are accessed and controlled by the control data from a micro controller. The control data are transmitted through the I2C bus. All timing control signals including the system clock are synchronized with the horizontal sync. Therefore there is a PLL circuitry on chip. 24-DIP-300 FEATURES ORDERING INFORMATION * * Build in 1K-byte SRAM 464 ROM fonts (448 standard fonts + 16 Multi-color fonts) * * * * * * * * * * * * * * * * * * * Full Screen Memory Architecture Wide range PLL available (15 kHz -- 120 kHz) Programmable vertical height of character Programmable vertical and horizontal positioning Character color selection up to 16 different colors Programmable background color (Up to 16 colors) Character blinking, bordering and shadowing Color blinking Character scrolling Fade-in and fade-out Row to row spacing control Window outline and shadowing Box drawing Character sizing up to four times 8 PWM DAC channels with 8-bit resolution 96 MHz pixel frequency from on-chip PLL I2C Protocol Data Transmission (Slave Address : BAH) OSD Vertical Bouncing Auto Detect / Correction Back Raster Blanking (Row Control) Device Package Operating Temperature 0C -- 70C S5D2501F 24-DIP-300 1 S5D2501F OSD PROCESSOR FOR MONITORS BLOCK DIAGRAM SDA 7 SCL 8 Data Receiver PWM 16 Data RAM Data 16 RAM (480 x 16) ROM Addr 9 Control 16 Data Font Control Single Color Multi-Color ROM ROM (448 x 18x12) (16x4 x 18x12) PWM0 9 PWM1 10 PWM2 11 PWM3 12 PWM4 13 PWM5 14 PWM6 15 PWM7 16 CLK HFLB 6 H-Pulse VFLB 17 Font 12 Data Font 12 Data 2 3 INT OSD_PLL V-Pulse 2 PWM Generator 3 4 PWM Register Frame Control Row Control Display Controller Display Control 2 2 R_OUT Control Register Output Stage 2 1 G_OUT 2 0 B_OUT 1 9 FBLK Frame Control Row Control H/V/CLK Control H/V/CLK Control Timing Controller 1 5 18 24 VCO_IN VREF1 VREF Figure 1. Functional Block Diagram . VSSA VDDA VSS VDD 2 OSD PROCESSOR FOR MONITORS S5D2501F PIN CONFIGURATIONS VSS-A VCO-IN VREF1 VREF VDD-A HFLB SDA SCL PWM0 PWM1 PWM2 PWM3 1 24 VDD_D INT R_OUT G_OUT B_OUT FBLK VSS_D VFLB PWM7 PWM6 PWM5 2 23 3 22 4 21 5 20 6 19 7 S5D2501F 18 17 16 8 9 10 15 11 14 12 13 PWM4 Figure 2. Pin Configurations 3 S5D2501F OSD PROCESSOR FOR MONITORS PIN DESCRIPTIONS Table 1. Pin Descriptions Pin No. 1 2 3 Signal VSS_A VCO_IN VREF1 Active I/O Input Input Ground (Analog Part) This voltage is generated at the external loop filter and goes into the input stage of the VCO. 1.26 V DC Voltage from the Bandgap Reference. Connected to ground through a resistor to make internal reference current (Typical 36 k for 27A) Bandgap Reference Voltage (Typical 1.26 V) +5 V Supply Voltage for Analog Part Horizontal Flyback Signal Serial Data (I 2C) Serial Clock (I2C) PWM DAC 0 Output PWM DAC 1 Output PWM DAC 2 Output PWM DAC 3 Output PWM DAC 4 Output PWM DAC 5 Output PWM DAC 6 Output PWM DAC 7 Output Vertical Flyback Signal Ground for Digital Part Fast Blank Signal Video Signal Output (B) Video Signal Output (G) Video Signal Output (R) Intensity Signal Output +5 V Supply Voltage for Dogital Part Description 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VREF VDD_A HFLB SDA SCL PWM 0 PWM 1 PWM 2 PWM 3 PWM 4 PWM 5 PWM 6 PWM 7 VFLB VSS_D FBLK B_OUT G_OUT R_OUT INT VDD_D Low Low - Input Input In/Out In/Out Output Output Output Output Output Output Output Output Input Output Output Output Output Output - 4 OSD PROCESSOR FOR MONITORS S5D2501F ABSOLUTE MAXIMUM RATINGS Value Parameters Maximum Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Power Dissipation NOTE: PKG Thermal Resistance : 64.2 C/W Symbol VDD VI TOPR TSTG PD Min. -20 -40 - Typ. - Max. 6.5 5.25 70 125 Unit V V C C - 1200 mW ELECTRICAL CHARACTERISTICS DC Electrical Characteristics (Ta = 25 C, VDD = 5 V) Table 2. DC Electrical Characteristics Parameters (Conditions) Supply Voltage Supply Current (No load on any output) Input Voltage Output Voltage (lout = 1mA) Input Leakage Current VCO Input Voltage Symbol VDD IDD VIH VIL VOH VOL IIL VVCO Min. 4.75 0.8VDD 0.8VDD -10 Typ. 5.00 2.5 Max. 5.25 25 VSS + 0.4 VSS + 0.4 10 Unit V mA V V V V A V 5 S5D2501F OSD PROCESSOR FOR MONITORS OPERATION TIMINGS Table 3. Operation Timings Parameters (Conditions) Symbol Min. Typ. Max. Unit Output Signal R/G/B_OUT, INT, FBLK (Ta = 25C VDDA = VDD = 5 V , CLOAD = 30pF) Rise Time Fall Time Input Signal HFLB, VFLB Horizontal Flyback Signal Frequency Vertical Flyback Signal Frequency I2C Interface SDA, SCL (Refer to Figure 3) SCL Clock Frequency Hold Time for start condition Set Up Time for stop condition Low Duration of clock High Duration of clock Hold Time for data Set Up Time for data Time between 2 access Fall Time of SDA Rise Time of both SCL and SDA fSCL ths tsus tlow thigh thd tsud tss tfSDA trSDA 500 500 400 400 0 500 500 300 20 kHz ns ns ns ns ns ns ns ns ns fHFLB fVFLB 120 200 kHz Hz tR tF 6 6 nsec nsec tss SD A ths SC L t sud t hd t high tlow Figure 3. I2C Bus Timing Diagram 6 OSD PROCESSOR FOR MONITORS S5D2501F FUNCTIONAL DESCRIPTIONS Data Transmission to the S5D2501F According to the I 2C protocol, the S5D2501F receives the data from a micro controller. The SDA line and the SCL line are shown in Figure 4. As shown in Figure 4, after the starting pulse, the slave address with R/W* bit and an acknowledge are transmitted in sequence, an internal register address of the S5D2501F is followed. The first 8-bit byte is the upper 8bits of the register address. The lower 8bits of the register address are followed after the second acknowledge. There is a data transmission format and are two address bit patterns in the S5D2501F as following. The slave address of the S5D2501F is BAH(in hexadecimal). Data Transmission Format Row Address -> Column Address -> Data Byte N -> Data Byte N+1 -> Data Byte N+2 -> .... Address Bit Pattern for Display Registers Data (a) Row Address Bit Pattern A15 X A14 X A13 X R3 - R0: Valid Data for Row Address A12 X A11 R3 A10 R2 A9 R1 A8 R0 (b) Column Address Bit Pattern A7 X A6 X A5 X C4 - C0: Valid Data for Column Address A4 C4 A3 C3 A2 C2 A1 C1 A0 C0 After addressing, data bytes are followed as the above data transmission format. The Figure 4 describes the data transmission with the I2C bus protocol. Figure 4. (a) SDA line and SCL line (Write Operation) Figure 4. (b)SDA line and SCL line (Read Operation) E E E E C C C C D D D D E D D D E D E D D D D E D C D C C C E D E E D E C EE EE C EE D D 7 S5D2501F OSD PROCESSOR FOR MONITORS Memory Map The display RAM is addressed with the row and column number in sequence. The display RAM consists of four register groups: Character & Attribute Registers, Row Attribute Registers, Frame Control Registers and PWM Control Registers. As the display area in a monitor screen is 30 columns by 15 rows, the related Character & Attribute Registers are also 30 columns by 15 rows. Each register contains a character address and an attribute corresponding to display location on a monitor screen. And one register is composed of 16 bits. The lower 9 bits select characters out of 464 ROM fonts. The upper 7 bits are assigned to give a character attribute to a selected font. Row Attribute Registers occupy the 31th column of Display RAM and provide the row attribute of a blank mode, raster color, raster color intensity, character color intensity, horizontal character size, vertical character size. Frame Control Registers and PWM Control Registers are located at the 16th row. The content of each register is described in Figure 5 and following register set. 00 01 02 Row 00 Row 01 27 28 29 30 Character & Attribute Registers (30 x 15 Character Display) Row 13 Row 14 Row 15 00 01 02 03 04 05 06 07 08 Frame Control PWM Control Registers Registers Figure 5. Memory Map of Display Registers Row Attribute Registers 8 OSD PROCESSOR FOR MONITORS S5D2501F ROM Fonts S5D2501F is able to supply 464 ROM fonts for describing an OSD icon. So a multi-language OSD icon can be generated. 448 fonts of 464 ROM fonts are standard fonts and 16 fonts are multi-color fonts as following figure. The standard font $000 is reserved for blank data. Each multi-color font consists of 4-color attribute ROM fonts as following figure. 0 1 E F 00 $000 $001 $00E $00F 01 $010 $011 $01E $01F Standard Fonts 1A $1A0 $1A1 $1AE $1AF 1B $1B0 $1B1 $1BE $1BF 1C $1C0 $1C1 $1CE $1CF Multi-Color Fonts $1C0 - INT $1C0 - B $1C0 - G $1C0 - R Figure 6. Array of ROM Fonts 9 S5D2501F OSD PROCESSOR FOR MONITORS Window , Window Shadowing and Bordering Window Start Position Row Spacing Row(font height) Row Spacing Shadow Vertical Width Bordering Width Window Stop Position Shadow Horizontal Width Scroll The scrolling function is to display or erase a character slowly from the top line to the bottom. The scrolling time is controlled by 'ScrT'bit of the frame control registers. If 'ScrT' bit is high, then the time is 1 sec. Otherwise, 0.5 sec. Character Bordering & Shadowing 10 OSD PROCESSOR FOR MONITORS S5D2501F Character Height Control Two examples of the height-controlled character are shown in the following figure. The height control is performed by repeating some lines. The repeating line-number comes from the equation below. [# of the repeating lines = 2 + N x M ] , where N = 1,2,3,... and M = round{14 /(CH[5:0]-18)}. If the M value is less than or equal to 1, all the lines of the standard font are repeated once or more. This is described as following. (i) If CH[5:0] is greater than 32, and less than or equal to 46 ( 32 < CH[5:0] 46 ), then all lines are repeated once or twice. The lines repeated twice are selected by the following equation. [# of the repeating lines = 2 + N x M ] , where N = 1,2,3,... and M= round{14/(CH[5:0]-32)}. (ii) If CH[5:0] is greater than 46, and less than or equal to 60 ( 46 < CH[5:0] 60 ), then all lines are repeated twice or three times. The lines repeated three times are selected by the following equation. [# of the repeating lines = 2 + N x M ] , where N = 1,2,3,... and M= round{14/(CH[5:0]-46)}. iii) If CH[5:0] is greater than 60, and less than or equal to 64 ( 60 < CH[5:0] 64 ), then all lines are repeated three or four times. The lines repeated four times are selected by the following equation. [# of the repeating lines = 2 + N x M ] , where N = 1,2,3,... and M= round{14/(CH[5:0]-60)}. The repeating line-number is limited to 16. 11 S5D2501F OSD PROCESSOR FOR MONITORS 12 D D E E D D D D D D D D D D D D D D CD C C CD C C E E OSD PROCESSOR FOR MONITORS S5D2501F PWM OUTPUT fPWM Internal reference pulse PWM OUTPUT 00100000 01000000 01100000 The frequency of PWM signal (fPWM) is dependent on the horizontal flyback signal frequency and horizontal mode (320dots/line, ...) as shown in the following table. Horizontal Mode 15kHz < Hf < 20kHz 20kHz < Hf < 35kHz 35kHz < Hf < 50kHz 50kHz < Hf < 65kHz 65kHz < Hf < 80kHz 80kHz < Hf < 95kHz 95kHz < Hf < 110kHz 110kHz < Hf < 120kHz (320/256) * (Hf/2) (640/256) * (Hf/4) (800/256) * (Hf/4) (320/256) * Hf (480/256) * (Hf/2) (480/256) * Hf (640/256) * (Hf/2) (800/256) * (Hf/2) 320 dots/line (fPWM) 480 dots/line (fPWM) 640 dots/line (fPWM) (640/256) * Hf 800 dots/line (fPWM) (800/256) * Hf 13 S5D2501F OSD PROCESSOR FOR MONITORS FRAME CONTROL & TIMING Figure 7 shows the composition of display frame with the OSD characters. HFLB HP[7:0] User can determine the dot frequency by the equation of H freq. x the number of horizontal resolution. And the number of horizontal resolution is determined by the bit9 - 8 (dot 1,dot 0) of the frame Control registers-1. If dot 0 = "0", dot 1 = "0", then the dot frequency is calculated by the equation of H freq. x 320. If the H freq. = 15 kHz, then the dot frequency is 15 kHz x 320 = 4.8 MHz. If dot 0 = "1", dot 1 = "1" and the horizontal frequency is 120 kHz, then the dot frequency is 120 kHz x 800 = 96 MHz. 96 MHz is the maximum clock frequency in this processor. 14 ]0:7[PV )stod 81 x 51(swoR 51 BLFV 30 Columns(=30 x 12 dots) OSD Characters Background Screen Figure 7. Frame Composition with the OSD Characters OSD PROCESSOR FOR MONITORS S5D2501F REGISTER DESCRIPTION Character & Attribute Register : Row00~14, Column00~29 F E D C B A 9 8 7 6 5 4 3 2 1 0 BINV BOX1 BOX0 B G R Blink/FINT C8 C7 C6 C5 C4 C3 C2 C1 C0 Character Attribute Character Code(464 Fonts) Row Attribute Register : Row00~14, Column30 F E BREN D C B A 9 8 7 6 5 4 3 2 1 0 - INTE CBli BOXE BORD SHA RB RG RR RINT CINT HZ1 HZ0 VZ1 VZ0 Raster Color Intensity Character Size Frame Control Register 0 : Row15, Column00 F E D C B A 9 8 7 6 5 4 3 2 1 0 - Fde FdeT VPOL HPOL WC WBOR WSHA - Erase EN ScrI ScrT Bli1 Bli0 BliT Frame Control Register 1 : Row15, Column01 F E D C B A 9 8 7 6 5 4 3 2 1 0 CP1 CP0 Fpll HF2 HF1 HF0 dot1 dot0 - FBLK CH5 CH4 CH3 CH2 CH1 CH0 PLL Control Character Height Control Frame Control Register 2 : Row15, Column02 F E D C B A 9 8 7 6 5 4 3 2 1 0 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 Horizontal Start Position Vertical Start Position Frame Control Register 3 : Row15, Column03 F E D C B A 9 8 7 6 5 4 3 2 1 0 RS2 RS1 RS0 RSB RSG RSR RSI STR3 STR2 STR1 STR0 STC4 STC3 STC2 STC1 STC0 Row Space Row Space Color Window Start Position Frame Control Register 4 : Row15, Column04 F E D C B A 9 8 7 6 5 4 3 2 1 0 - BW1 BW0 HW1 HW0 VW1 VW0 SPR3 SPR2 SPR1 SPR0 SPC4 SPC3 SPC2 SPC1 SPC0 Window Stop Position PWM Registers : Row15, Column05~08 F E D C B A 9 8 7 6 5 4 3 2 1 0 MSB LSB MSB LSB Channel 2/4/6/8 Channel 1/3/5/7 `-' ; Don't care bit 15 S5D2501F OSD PROCESSOR FOR MONITORS Table 4. Register Description Registers Character & Attribute Register (Row 00--14, Column 00--29) Bits C8--C0 (Bit 8--0) Blink (Bit 9) Description Character Code Address of 464 ROM Fonts. Character Blinking. Set this bit to activate the blinking effect. The blinking period is set by the 'Bli T' bit and the duty is selected by the 'Bli 0' and 'Bli 1' bits. If `INTE' bit is high, this bit controls the font intensity combined with `INTE', 'RINT' and `CINT' as following table. INTE Blink RINT CINT 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 0 1 Function Normal Blink Normal Character Intensity Raster Intensity Character & Raster Intensity B,G,R (Bit C--A) Character Color is determined by these bits. 8 colors can be selected and the color intensity of a character is given by 'CINT' bit of Row Attribute Regisers. So you can select up to 16 colors. If a multi-color font is selected, this bits must be set to all 0's. Character Box Drawing. The combinations of this two bits generate four different box drawing modes as following. The following example is the case that box dawing is activated with the font 'A'. BOX0 0 BOX1 1 BOX 1, BOX0 (Bit E, D) 0 BOX OFF 1 * Bit F -- D (RB/RG/RR) is also used for raster color by setting the 'BOXE' bit low. Raster color of a font is determined by this bits if the 'BOXE' bit is low. Priority of raster color selected here is higher than that of row attribute. 16 OSD PROCESSOR FOR MONITORS S5D2501F Table 4. Register Description (Continued) Registers Character & Attribute Register Row Attribute Register (Row 00 -- 14, Column 30) Bits BINV (Bit F) VZ1,VZ0 (Bit 1, 0) Description Box Inversion. The box drawing activated by the bit E and D is changed to white box from black and conversely. Vertical Character Size Control. Vertical character size is determined by the combinations of this two bits as following table. VZ1 0 0 1 1 VZ0 0 1 0 1 Vertical Character Size 1X 2X 3X 4X HZ1,HZ0 (Bit 3, 2) Horizontal Character Size Control. The horizontal character size is determined by the combinations of this two bits as following table. HZ1 0 0 1 1 HZ0 0 1 0 1 Horizontal Character Size 1X 2X 3X 4X CINT (Bit 4) RINT (Bit 5) RB,RG,RR (Bit 8--6) Character Color Intensity. If INTE, Blink and this bit is set, the color intensity of characters in the same row is high. Raster Color Intensity. If INTE, Blink and this bit is set, the color intensity of rasters in the same row is high Raster Color is determined by these bits. 8 colors can be selected and the color intensity of a character is given by 'RINT' bit of Row Attribute Registers. So you can select up to 16 colors. Character Shadowing. Set this bit to activate characters shadowing. Character Bordering. Set this bit to activate characters bordering. SHA (BIT 9) BORD (Bit A) 17 S5D2501F OSD PROCESSOR FOR MONITORS Table 4. Register Description (Continued) Registers Row Attribute Register Bits BOXE (Bit B) Description BOX Enable. If this bit is set, Bit F-D in the Character & Attribute Registers are used for the box-drawing function. Otherwise,those are used for raster color of a font. Even though the raster color attribute is given by Bit 8-6 in the row attribute registers, the priority of Bit F-D in the character & attribute registers is higher. Color Blink Enable. If this bit is high, color blinking effect is activated. The color effect is to repeat color inversion between character and raster. Color blinking time and the duty is controlled by Bil T, Bil 1 and Bli 0. Intensity Enable. If this bit and Blink bit(CHARACTER ATTRIBUTE) is high, character and raster intensity can be controlled. Back Raster Enable. If this bit is high and back raster color is black, back raster color is blank. Reserved CBli (Bit C) INTE (Bit D) BREN (Bit E) Bit F 18 OSD PROCESSOR FOR MONITORS S5D2501F Table 4. Register Description (Continued) Registers Frame Control Register 0 (Row 15, Column 00) Bits Bli T (Bit 0) Bli 1,Bli 0 (Bit 2,1) Description Blink Time Control. If this bit is high, the blink time is 0.5 sec. Otherwise, 1 sec. Blinking Duty Control. The blinking duty is controlled by the combination of this two bits as following. Bli 1 0 0 1 1 ScrT (Bit 3) Scrl (Bit 4) EN (Bit 5) Erase (Bit 6) WSHA (Bit 8) WBOR (Bit 9) WC (Bit A) HPOL (Bit B) VPOL (Bit C) FdeT (Bit D) Fde (Bit E) Bit F Bli 0 0 1 0 1 Blinking Duty Blink Off Duty 25% Duty 50% Duty 75% Scroll Time Control. If this bit is high, the scroll time is 1 sec. Otherwise, 0.5 sec. Scroll Enable. The scroll display is activated by setting this bit high. OSD Enable. The character display is controlled by this bit. If this bit is high, OSD is enable. Otherwise, disable. RAM Erasing. RAM data are erased by setting this bit. Window Shadowing. Set this bit to activate window shadowing. Window Bordering. Set this bit to activate window bordering. White/black selection of window border and shadow. If this bit is high, the color of window border and shadow is white. Otherwise, black. Polarity of Horizontal Fly Back Signal. Positive 1, Negative 0 Polarity of Vertical Fly Back Signal. Positive 1, Negative 0 Fade-in and fade-out Time Control. If this bit is high, the time is 1 sec. Otherwise, 0.5 sec. Fade-in and fade-out Enable. The fade-in and fade-out effect is activated by setting this bit high. Reserved. 19 S5D2501F OSD PROCESSOR FOR MONITORS Table 4. Register Description (Continued) Registers Frame Control Register 1 (Row 15, Column 01) Bits CH5--CH0 (Bit 5--0) Description Character Height Control. The vertical character size is determined by the bit 'VZ1' and VZ0'. This six bits are available to get a proper character height by setting a binary value. According to the value made by this six bits, the character height is determined. If the value is 32, the number of vertical pixel of character font is 32. Eventually, the character height is expanded from 18 to 63. The binary vlaue must be greater than 18. It determines the configuration of FBLK output pin. When it is clear, FBLK pin outputs high during displaying characters or rasters. Otherwise,FBLK pin outputs high only during displaying characters. This two bits determine the number of dots per horizontal line. Refer to following table. dot 1 0 0 1 1 HF2--HF0 (Bit C--A) FPLL (Bit D) Frame Control Register 1 (Row 15, Column 01) CP 1,CP 0 (Bit F,E) dot 0 0 1 0 1 No. of Dots 320 dots/line 480 dots/line 640 dots/line 800 dots/line FBLK (Bit 6) dot 1,dot 0 (Bit 9,8) These three bits decide horizontal frequency range (region). Please refer to Application Note for more information. If this bit is high, the VCO block of OSD_PLL operates on full range (4 MHz - 96 MHz). This bit controls charge pump output current. CP 1 0 0 1 1 CP 0 0 1 0 1 Charge Pump Current 0.75mA 1 mA 1.25mA 1.5 mA Frame Control Register 2 (Row 15, Column 02) VP7--VP0 (Bit 7--0) HP7--HP0 (Bit F--8) Vertical Start Position Control. It means the top margin height from the V-sync reference edge. ( = VP[7:0] x 4 ) Horizontal Start Position Control. It means the horizontal display delay from the H-sync reference edge to the 1'st pixel position of characters. ( = HP[7:0] x 6 ) 20 OSD PROCESSOR FOR MONITORS S5D2501F Table 4. Register Description (Continued) Registers Frame Control Register 3 (Row 15, Column 02) Bits STC 4 --STC 0 STR 3 --STR 0 RSI RSR,RSG, RSB RS2--RS0 (Bit F--D) Frame Control Register 4 (Row 15, Column 04) SPC 4-- SPC 0 SPR 3-- SPR 0 VW 1, 0 HW 1, 0 BW 1, 0 PWM Registers (Row 15, Column 05 - 08) Bit 7-- 0 Bit F--8 Description Window Start Column Position. It means the column address that window starts from. Window Start Row Position. It means the row address that window starts from. Row Space Color Intensity. Row Space Color Attribute. Row Space. It means the line number between a character row and the next row. The defaut value is 0. (line number for spacing = RS[2:0] x 2) Window Stop Column Position. It means the column address that window stops on. Window Stop Row Position. It means the row address that window stops on. Vertical width of window shadowing. Horizontal width of window shadowing. Width of window bordering. This 8-bit value decides the output duty cycle and waveforms of PWM for channel 1,3,5 and 7. This 8-bit value decides the output duty cycle and waveforms of PWM for channel 2,4,6 and 8. 21 S5D2501F OSD PROCESSOR FOR MONITORS APPLICATION CIRCUIT VCC=5V + 100uF 104 1 VSSA VDD 24 + 100uF 104 INT 5.6K 101 392 2 VCO_IN INT 23 400 R_OUT 36K 3 VREF1 R_OUT 22 400 4.7uF 103 Bead 1uH + + G_OUT 4 VREF G_OUT 21 400 B_OUT 100uF 104 5 VDDA B_OUT 20 400 VCC FBLK 470 6 VCC HFLB FBLK 19 400 HFLB 120 120 102 2N3904 4.7K 4.7K 2K 7 S5D2501F KS2501 SDA VSS 18 VFLB 6.2K 2K 8 SCL VFLB 17 120 2.2nF 2K 9 + 1 SDA 2 SCL + 10uF 2K 10uF 2K PWM0 PWM7 16 2K + 10uF 10 PWM1 PWM6 15 2K + 10uF 11 + 10uF 2K PWM2 PWM5 14 2K + 10uF 12 + 10uF PWM3 PWM4 13 2K + 10uF 22 |
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